1. Field of the Invention:
The present invention relates to: a solid-state image capturing device capable of making the reading characteristic in each of a plurality of pixel sections consistent when an electric charge detection section is shared by the plurality of pixel sections; a method for manufacturing the solid-state image capturing device; and an electronic information device having, for example, a digital camera (e.g., digital video camera and digital still camera) or an image input device (e.g., image input camera, scanner, facsimile and cellar phone device equipped with a camera) using the solid-state image capturing device as an image capturing section therein.
2. Description of the Related Art:
As a conventional solid-state image capturing device, a CMOS-type (complementary metal oxide semiconductor) solid-state image capturing device is known, in which the following constituents are provided on a substrate and a plurality of each of the constituents is provided in two dimensions: a plurality of light receiving sections for converting incident light into signal electric charge and accumulating the signal electric charge; transfer sections for reading the signal electric charge accumulated in the respective light receiving sections; reading gate electrodes provided over the respective transfer sections in order to control the reading of the signal electric charge accumulated in the respective light receiving sections; and an electric charge detection section shared by the light receiving sections of two or more pixels in order to detect the read signal electric charge.
Hereinafter, the conventional CMOS-type solid image capturing device will be described with reference to FIGS. 7 to 10. First, a structural example of the conventional CMOS-type solid image capturing device will be described in detail with reference to FIG. 7.
Portion (a) of FIG. 7 is a top view showing a structure of the conventional CMOS-type solid image capturing device. Portion (b) of FIG. 7 is a cross-sectional view of Portion (a) of FIG. 7 cut by a line A-A′. Portion (c) of FIG. 7 is a cross-sectional view of Portion (a) of FIG. 7 cut by a line B-B′. Portion (d) of FIG. 7 is a view showing potential, of Portion (a) of FIG. 7 cut by a line A-A′, at the time of electric charge transfer. Portion (e) of FIG. 7 is a view showing potential, of Portion (a) of FIG. 7 cut by a line B-B′, at the time of electric charge transfer.
In Portions (a) to (a) of FIG. 7, for each unit of two pixel sections, light receiving sections 101a and 101b; reading gate electrodes 102a and 102b; and an electric charge detection section 103 shared by the light receiving sections 101a and 101b are provided in the conventional solid-state image capturing device 100. Further, a reset gate electrode 104 and a reset drain section 105 for resetting signal electric charge of the electric charge detection section 103 are provided in this conventional solid-state image capturing device 100.
As each of the light receiving sections 101a and 101b, an electric charge accumulation region 113 made of an N-type impurity diffusion layer is provided on a P-type diffusion layer 111 over an N-type semiconductor substrate 110. A P+region 114 is provided at the top of each of the light receiving sections 101a and 101b. Each of the reading gate electrodes 102a and 102b is provided over a P-type impurity region 112 with a gate oxide film 116 therebetween wherein the P-type impurity region 112 makes up a transfer section. The reading gate electrodes 102a and 102b are provided in order to control a reading voltage of the respective transfer sections and the like. In addition, the electric charge detection section 103 is made up of an N-type impurity region 115.
An operation of the conventional CMOS-type solid image capturing device 100 having the structure described above will be described.
First, light (subject light) which is incident on an image capturing region of the CMOS-type solid-state image capturing device 100 is photoelectrically converted into signal electric charge at the light receiving sections 101a and 101b, respectively. The signal electric charge photoelectrically converted at the light receiving sections 101a and 101b respectively is once accumulated in the respective electric charge accumulation regions 113 of the light receiving sections 101a and 101b. 
Next, a predetermined voltage is applied to the reading gate electrodes 102a and 102b so as to read the signal electric charge accumulated in each of the respective light receiving sections 101a and 101b to the electric charge detection section 103 via the P-type impurity region 112 of the transfer section.
An image capturing signal can be obtained by amplifying potential corresponding to the signal electric charge read to each of the electric charge sections 103.
A method for manufacturing the conventional CMOS-type solid-state image capturing device 100 will be described with reference to FIGS. 7 and 8.
Portions (a) to (d) of FIG. 8 each show a top view for explaining the method for manufacturing the conventional solid-state image capturing device 100.
As shown in Portions (b) and (c) of FIG. 7, in manufacturing the conventional CMOS-type solid-state image capturing device 100, first, an ion implantation process with boron or the like and a thermal treatment are performed on the N-type semiconductor substrate 110 so as to form the P-type diffusion layer (P well) 111.
Next, as shown in Portion (a) of FIG. 8, a thermal oxide film (not shown) for separating an active region and an inactive region is formed by using a resist pattern 121 (having an opening therein) is formed on the P-type diffusion layer (P well) 111.
Further, as shown in Portion (b) of FIG. 8, an ion implantation process with boron or the like is preformed on the P-type diffusion layer (P well) 111 by using a resist pattern 122 (having an opening therein). As a result, as shown in Portions (b) and (c) of FIG. 7, the impurity region 112 for controlling the reading voltage of the transfer section is formed.
Next, a gate oxide film 116 shown in Portions (b)and (c) of FIG. 7 is formed on the surface of the N-type semiconductor substrate 110 by performing a thermal oxidation treatment at a temperature of 1000 degrees Celsius to 1100 degrees Celsius in an atmosphere Of O2 gas and HCl gas.
Thereafter, a multi-layered film, in which, for example, a poli-silicon film and a W (tungsten) film are layered, is formed by performing a CVD (Chemical Vapour Deposition) method and a sputtering method. Then, a dry etching is performed on the resultant film. As a result, the reading gate electrodes 102a and 102b and the reset gate electrode 104 are formed, as shown in Portion (c) of FIG. 8.
Further, as shown in Portion (d) of FIG. 8, an ion implantation process with phosphorus or arsenic and a thermal treatment are performed, by using a resist pattern 123 (having an opening therein) on a location corresponding to each of the light receiving sections 101a and 101b on the gate oxide film 116. As a result as shown in Portions (b) and (c) of FIG. 7, the N-type impurity region is formed wherein the N-type impurity region will become the electric charge accumulation region 113 of each of the light receiving sections 101a and 101b. The electric charge accumulation regions 113 are formed in a manner of self-alignment with respect to the respective reading gate electrodes 102a and 102b. 
Further, an ion implantation process with arsenic or the like is performed by using a pattern (not shown) so as to form the electric charge detection section 103 (N-type impurity region 115) and the reset drain section 105, as shown in Portions (a) to (c) of FIG. 7.
Thereafter, an ion implantation process with boron or the like is performed by using a pattern (not shown) so as to form the surface P+ region 114 of each of the light receiving sections 101a and 101b, as shown in Portions (a) to (c) of FIG. 7.
Herein, shown in Portions (a) to (c) of FIG. 7, the structure having each electric charge detection section 103 shared by the two light receiving section 101a and 101b respectively arranged in upper and lower positions in a plane will be described.
When each electric charge detection section 103 is shared by the two light receiving section 101a and 101b respectively arranged in the upper and lower positions, it is possible to secure a large size of the light receiving sections 101a and 101b due to sharing of the electric detection section 103, compared to the case when the electric charge detection section 103 is provided for each pixel. Thus, sensitivity characteristic to incident light can be improved.
As described above, in the conventional solid-state image capturing device 100 in which the electric charge detection section 103 is shared by a plurality of light receiving sections 101a and 101b, an image capturing signal with good quality can be obtained by controlling an electric charge accumulation, electric charge reading and reset operation, with a good timing, at the light receiving section 101a and 101b respectively arranged in the upper and lower positions when the electric charge reading operation is performed.
For example, Reference 1 discloses a solid-state image capturing device capable of: completely transferring signal electric charge without generating any depression (corresponding to a depression 117 shown in Portion (b) of FIG. 7) in the potential of the transfer section at the time of electric charge transfer; and suppressing the occurrence of a residual image, by forming an overlap of the electric charge accumulation layer of each of the light receiving sections and the surface P+ layer with an excellent controllability.
[Reference 1] Japanese Laid-Open Publication No. 11-126893